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| rev.1.00 S1R72V27 data sheet
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit a nd, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2007, all rights reserved. scope this document applies to the S1R72V27 usb 2.0 device/host controller lsi. S1R72V27 data sheet (rev. 1.00) epson i contents 1. over view.................................................................................................................... ........................ 1 2. feat ures.................................................................................................................... ......................... 2 3. block diagram............................................................................................................... .................... 3 4. explanati on of func tions .................................................................................................... ............. 4 4.1 power s upply ................................................................................................................... .......... 4 4.2 reset .......................................................................................................................... ................ 5 4.2.1 hard re set ..................................................................................................................... ... 5 4.2.2 soft reset..................................................................................................................... ..... 5 4.3 clock .......................................................................................................................... ................ 5 4.4 power m anagem ent ............................................................................................................... .... 6 4.5 cpu-i/f........................................................................................................................ ............... 7 4.6 usb device i/f ................................................................................................................. .......... 7 4.6.1 speed mode and tr ansfer ty pe ........................................................................................ 7 4.6.2 resour ces ...................................................................................................................... ... 7 4.6.2.1 endpoi nt ....................................................................................................................... .. 7 4.6.2.2 fifo ........................................................................................................................... .... 8 4.6.3 data flow ...................................................................................................................... .... 8 4.6.4 usb device port ex ternal ci rcuits .................................................................................... 9 4.7 usb host i/f................................................................................................................... .......... 10 4.7.1 speed mode and tr ansfer ty pe ...................................................................................... 10 4.7.2 resour ces ...................................................................................................................... .10 4.7.2.1 channel s ...................................................................................................................... 1 0 4.7.2.2 fifo ........................................................................................................................... .. 10 4.7.3 data flow ...................................................................................................................... .. 10 4.7.4 usb host port exte rnal circ uits ...................................................................................... 12 4.8 fifo ........................................................................................................................... .............. 12 5. terminal la yout diagrams .................................................................................................... ......... 13 6. terminal functi ons .......................................................................................................... ............... 15 7. electrical ch aracteristics .................................................................................................. ............. 18 7.1 absolute maxi mum rati ngs ...................................................................................................... 1 8 ii epson S1R72V27 data sheet (rev. 1.00) 7.2 recommended operat ing condi tions....................................................................................... 18 7.3 dc characte ristics............................................................................................................. ....... 19 7.3.1 current cons umptio n ...................................................................................................... 19 7.3.2 input characte ristic s........................................................................................................ 21 7.3.3 output charac teristic s ..................................................................................................... 22 7.3.4 terminal capa citanc e ...................................................................................................... 23 7.4 ac characte ristics............................................................................................................. ....... 24 7.4.1 reset ti ming ................................................................................................................... 24 7.4.2 clock timing................................................................................................................... .24 7.4.3 cpu/dma i/f acce ss timing ........................................................................................... 26 7.4.3.1 specifications for cvdd = 1.65 v to 3.6 v ................................................................... 26 7.4.3.2 specifications when limited to cvdd = 3.0 v to 3.6 v (relaxed specifications).......... 27 7.4.4 usb i/f timing ................................................................................................................ 2 8 8. connecti on examples ......................................................................................................... ........... 29 8.1 cpu i/f connecti on exampl e................................................................................................... 29 8.2 usb i/f connecti on exampl e ................................................................................................... 30 9. product codes ............................................................................................................... ................. 31 10. external dime nsion diagrams ................................................................................................ ..... 32 1. overview S1R72V27 data sheet (rev. 1.00) epson 1 1. overview the S1R72V27 is a usb host/device controller lsi that supports the usb 2.0 high-speed mode. a single usb port can be operated as a usb host or usb device depending on how control is switched. this lsi maintains high compatibility with the s1r72v17 but includes additional functions such as support for usb host isochronous transfers. 2. features 2 epson S1R72V27 data sheet (rev. 1.00) 2. features < 3. block diagram S1R72V27 data sheet (rev. 1.00) epson 3 3. block diagram usb fifo cpu i/f controller xrd xi xo usb fifo controller dma controller xwrh xwrl ca[8:1] cd[15:0] xcs xint channel/endpoint xdack xdreq osc xbel host sie vbusflg vbusen device sie dp dm mtm r1 vbus pll clkin test mux tsten atpgen burnin xreset figure 3-1 overall block diagram 4. explanation of functions 4 epson S1R72V27 data sheet (rev. 1.00) 4. explanation of functions for details of the register names used in the following discussion, refer to the technical manual for this lsi. 4.1 power supply this lsi has three power supply systems and a common gnd. the power supply systems consist of hvdd (3.3 v) for the usb i/o power supply, cvdd (3.3 v to 1.8 v) for the cpu i/f power supply, and lvdd (1.8 v) for internal circu its and test i/o. (see figure 4-1.) i o cpu -i/f fifo sie mtm cpu usb lvdd hvdd cvdd 1.8v to 3.3v 1.8v 3.3v test io figure 4-1 S1R72V27 power supply circuit diagram the sequence of steps for turning the power supplies on and off are described below. this lsi cannot be operated with only the lvdd or cvdd power supplies turned on or off. the hvdd can be turned off if the lvdd or cvdd power supplies are on. the synchronous register cannot be accessed while hvdd is off, since the pll does not operate. also, the following restrictions apply to th e sequence for turning the cvdd/hvdd i/o power supplies and lvdd internal power supply on or off. there are no restrictions on the sequence for turning the cvdd and hvdd power supplies on or off. ? the lvdd must be turned on before turning on the cvdd and hvdd power supplies. ? in the powering off sequence, the cvdd and hvdd must be turned off before turning off the lvdd. if power supply circuit characteristics or the power supply load make this sequence impossible to follow, the cvdd or hvdd must not be on for more than 1 second while the lvdd is off. 4. explanation of functions S1R72V27 data sheet (rev. 1.00) epson 5 4.2 reset this lsi includes a hard reset function using the external xreset terminal and a soft reset function using register settings. 4.2.1 hard reset start up from reset status when power is turned on, then cancel the reset after confirming power on. 4.2.2 soft reset circuits related to the usb port or individual internal usb analog macros can be reset via software. this lsi can be soft reset using the chipreset.allreset bit. the chipreset.resetmtm bit is used to reset us b analog macros. note, however, that analog macros should only be reset in the sleep state. 4.3 clock this lsi contains an internal oscillator and feedback resistor (1 m ? ) and supports clock generation using an external oscillator. external clock input is supported via the clkin terminal. the oscillator frequency supports 12 mhz or 24 mhz using the internal oscillator. frequencies of 12, 24, or 48 mhz are supported via the external input. figure 4-2 shows a typical connection arrangement for an oscillation circuit. contact the oscillator manufacturer to determine circuit constants, as cd, cg, and rd in the oscillator circuit must be matched, based on the oscillator. xi xo cd rd cg figure 4-2 clock generation using the in ternal oscillator and external oscillator 4. explanation of functions 6 epson S1R72V27 data sheet (rev. 1.00) 4.4 power management this lsi includes a power mana gement function featuring two power management states, sleep and active, together with the cpu_cut power management state. (see figure 4-3.) all function blocks are active in the active st ate, whereas only the bare minimum circuits necessary for restarting from standby mode are ac tive in sleep state. cpu_cut mode minimizes power consumption attributable to the cpu-i/f input buffer. active cpu -i/f fifo sie utm osc sleep cpu -i/f* fifo sie utm osc cpu_cut cpu -i/f** fifo sie utm osc active inactive * the cpu-i/f is only partially active in sleep state. the asynchronous access register can be accessed. ** cpu-i/f operation is suspended in cpu_cut to minimize power consumption attributable to the i/o input buffer. figure 4-3 power management states 4. explanation of functions S1R72V27 data sheet (rev. 1.00) epson 7 4.5 cpu-i/f this lsi is connected to the cpu via a 16-bit interface. endian settings can be set as big endian or little endian in 16-bit steps. fo r big endian, registers with even addresses can be accessed above the bus (cd[15:8]), while registers with odd addresses can be accessed below the bus (cd[7:0]). for little endian, registers with even addresses can be accessed below the bus (cd[7:0]), while registers with odd addresses can be accessed above the bus (cd[15:8]). the bus mode can be set to either strobe mode for access using high/low strobe (xwrh/xwrl) or byte enable mode for access using high/low byte enable (xbeh/xbel) for writing the first or last 8 bits. endian and bus mode is set by the cpuif_mode register immediately cancelling of hard reset. the cpu-i/f on this lsi incl udes 1-ch dma (slave). the registers that can be accessed will depend on the power management state. for details, refer to the lsi technical manual. 4.6 usb device i/f this lsi supports high-speed specification usb device functions complying with the usb 2.0 (universal serial bus specification revision 2.0) standards. 4.6.1 speed mode and transfer type this lsi?s usb device function supports hs (480 mbps) and fs (12 mbps) speed modes. the speed mode is set automatically by the sp eed negotiation performed when resetting the bus. for example, hs transfer mode is sel ected automatically by speed negotiation if connected to a usb host that supports hs speed mode. in addition, the register can be set so that fs speed mode is always selected in speed negotiations. all transfer types stipulated under the usb 2.0 standard are supported, including control transfers (endpoint 0), bulk transfers, inte rrupt transfers, and is ochronous transfers. 4.6.2 resources 4.6.2.1 endpoint this lsi?s usb device function includes endpoint 0 and five standard endpoints. endpoint 0 supports control transfers. the standard endpoints support bulk transfers, interrupt tran sfers, and isochronous transfers. the standard endpoint numbers, maximum packet size, and transfer direction (in/out) can be set as desired. 4. explanation of functions 8 epson S1R72V27 data sheet (rev. 1.00) 4.6.2.2 fifo the lsi ports include 4.5 kb of fifo for use with usb data transfers. this forms the data transfer route with usb. the fifo capacity of each endpoint can be assigned as desired by the soft ware. for example, performance can be improved by assigning a sufficient size fifo area to the endpoints for bulk transfers. 4.6.3 data flow endpoints are assigned to usb fifo areas on a one-to-one basis, and responses are returned to usb transactions automatical ly, depending on effective usb fifo free capacity (for out transfers) or effective data quantity (for in transfers). this means the software does not need to be directly involv ed in individual transactions, allowing usb data transfers to be controlled as data flows at the usb fifo. usb fifo endpoint usb host i n t o k e n d a t a q u a n t i t y < m a x p k t s i z e n a k h a n d s h a k e i n t o k e n d a t a q u a n t i ty > = m a x p k ts i z e d a t a p a c k e t a c k h a n d s h a k e cpu w r i t e f i f o _ e m p t y f i f o _ e m p t y w r i t e i n t o k e n d a t a q u a n t i t y < m a x p k t s i z e write read in transaction (nak response) in transaction (data reply) in transaction (nak response) t r a n s f e r s e n t n a k h a n d s h a k e f i f o _ f u l l f i f o _ f u l l i n t o k e n d a t a q u a n t i t y > = m a x p k t s i z e d a t a p a c k e t a c k h a n d s h a k e in transaction (data reply) empty data figure 4-4 typical data flow (with fifo assigned for maxpktsize and in transfer) 4. explanation of functions S1R72V27 data sheet (rev. 1.00) epson 9 usb fifo endpoint usb host p i n g t o k e n f r e e q u a n t i t y > = m a x p k t s i z e a c k h a n d s h a k e o u t t o k e n cpu f i f o _ e m p t y p i n g t o k e n f r e e q u a n t i t y < m a x p k t s i z e read write ping transaction (ack response) out transaction (data receipt) ping transaction (nak response) t r a n s f e r r e c e i v e d n a k h a n d s h a k e f i f o _ f u l l f i f o _ e m p t y p i n g t o k e n f r e e q u a n t i t y > = m a x p k t s i z e ping transaction (ack response) empty data d a t a p a c k e t n y e t h a n d s h a k e r e a d a c k h a n d s h a k e note: ping transactions are performed only in high speed mode. figure 4-5 typical data flow (with fifo assigned for maxpktsize and out transfer) 4.6.4 usb device port external circuits the lsi usb port 0 has internal fs and hs device termination resistors, eliminating the need for the components normally used to adjust impedance. this allows a dp/dm line to be connected directly between the lsi terminal and the connector. note that the appropriate components must be used to ensure static electricity protection and to implement emi precautions. the vbus terminal uses a 5 v input and does not require external voltage conversion. a protection circuit is recommended, since certain commercially-available usb host and hub products may apply surge voltages exceeding vbus ratings. refer to the separately provided pcb desi gn guidelines for s1r72v series usb 2.0 hi-speed. 4. explanation of functions 10 epson S1R72V27 data sheet (rev. 1.00) 4.7 usb host i/f the lsi usb port 0 and port 1 support high-speed specification usb host functions complying with the usb 2.0 (universal serial bus specification revision 2.0) standards. 4.7.1 speed mode and transfer type this lsi?s usb host function supports hs ( 480 mbps), fs (12 mbps) and ls (1.5 mbps) speed modes. the speed mode is automatically set by speed negotiations performed on resetting the bus. all transfer types stipulated in the usb 2.0 standard are supported, including control transfers, bulk transfers, interrupt tr ansfers, and isochronous transfers. 4.7.2 resources 4.7.2.1 channels in the lsi usb host functions, sets of register settings for transfers with end points on a one-to-one basis are called channels. the lsi usb host function features one dedicated channel for control transfers, one dedicated channel for bulk transfers, and four general channels that support bulk transfers, interrupt transfers, and isochronous transfers. the endpoint number, maximum packet size, and transfer direction (in/out) can be set as desired for all channels. transfers are also possible for a numbe r of endpoints exceeding the channel number using software-based time-multiplexing for the channels. 4.7.2.2 fifo each port on the lsi includes 4.5 kb of fifo for use with usb data transfers. this forms the data transfer route wi th usb. the fifo capacity for each channel can be assigned as desired by the software. for example, to improve performance, assign a fifo area of ad equate size to the endpoints for bulk transfers. 4.7.3 data flow the channels are assigned to fifo areas on a one-to-one basis. transactions are sent automatically to usb, depending on the fifo effective free capacity (for in transfers) or effective data quantity (for out transfers). the software does not need to be directly involved in individual transactions, allowing usb data transfers to be controlled as data flow at the fifo. 4. explanation of functions S1R72V27 data sheet (rev. 1.00) epson 11 fifo cpu channel usb device n a k h a n d s h a k e i n t o k e n f r e e q u a n t i t y > = m a x p k t s i z e f r e e q u a n t i t y < m a x p k t s i z e t r a n s f e r r e c e i v e d f r e e q u a n t i t y > = m a x p kt s i z e f i f o _ e m p t y read write f i f o _ f u l l f i f o _ e m p t y empty data r e a d d a t a p a c k e t i n t o k e n a c k h a n d sh a k e i n t o k e n n a k h a n d s h a k e in transaction (nak response) in transaction (nak response) in transaction (data reply) figure 4-6 typical data flow (with fifo assigned for maxpktsize and in transfer) fifo channel usb device d a t a q u a n t i t y < m a x p k t s i z e d a t a q u a n t i t y > = m a x p k t s i z e cpu w r i t e f i f o _ e m p t y f i f o _ e m p t y w r i t e d a t a q u a n t i t y < m a x p k t s i z e write read t r a n s f e r s e n t f i f o _ f u l l f i f o _ f u l l d a t a q u a n t i t y > = m a x p k t s i z e o u t t o k e n d a t a p a c k e t a c k h a n d s h a k e o u t t o k e n d a t a p a c ke t a c k h a n d s h a k e empty data out transaction out transaction t r a n s f e r s e n t figure 4-7 typical data flow (with fifo assigned for maxpktsize and out transfer) 4. explanation of functions 12 epson S1R72V27 data sheet (rev. 1.00) 4.7.4 usb host port external circuits the lsi ports have internal usb host termination resistors, including an hs termination resistor, eliminating the need for the external components normally used to adjust impedance. this allows a dp/dm line to be connected between the lsi terminal and the connector. note that the appropriate components must be used to ensure static electricity protection and to implement emi precautions. an external vbus control component is required for the vbus. 4.8 fifo the lsi includes 4.5 kb of usb fifo for use with usb data transfers. the usb fifo capacity for each endpoint or channel can be assigned as desired using the register settings. transfers are possible between the us b-i/f and cpu-i/f via the usb fifo. 5. terminal layout diagrams S1R72V27 data sheet (rev. 1.00) epson 13 5. terminal layout diagrams burnin lvdd xi xo vss vss clkin cvdd n.c. cd15 cd14 cd13 cd12 cd11 cvdd vss cd10 cd9 lvdd vss 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 n.c. 61 40 atpgen n.c. 62 39 cd8 n.c. 63 38 cd7 n.c. 64 37 cd6 lvdd 65 36 cd5 vss 66 35 cd4 r1 67 34 cd3 vss 68 33 lvdd n.c. 69 32 vss hvdd 70 31 cvdd dm 71 30 cd2 vss 72 29 cd1 dp 73 28 cd0 hvdd 74 27 xdack vbus 75 26 xdreq lvdd 76 25 xwrl vss 77 24 xwrh n.c. 78 23 xrd n.c. 79 22 xcs n.c. 80 21 xint 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lvdd vss vbusflg vbusen hvdd xreset xbel ca1 ca2 ca3 ca4 vss cvdd ca5 ca6 ca7 ca8 testen lvdd vss figure 5-1 qfp package terminal layout diagram (qfp14-80) 12345678 a nc lvdd dp dm hvdd r1 lvdd burnin a b vbusflg vss hvdd vss vss vss vss xi b c vbusen hvdd vbus ca1 ca3 cd15 lvdd xo c d xreset xbel ca5 cd13 cvdd clkin d e ca2 ca4 xint cd4 cd11 cd14 e f ca7 ca8 xwrh xdack cd3 cd7 cd10 cd12 f g ca6 lvdd xrd xdreq cd1 cd6 vss cd9 g h testen xcs xwrl cd0 cd2 cd5 cd8 atpgen h 12345678 top view figure 5-2 bga package terminal layout diagram (pfbga5ux60) 5. terminal layout diagrams 14 epson S1R72V27 data sheet (rev. 1.00) 123456789 a nc lvdd hvdd dp dm hvdd r1 lvdd nc a b vss vss vbus vss vss vss vss vss xi b c vbusflg hvdd lvdd xbel ca1 cvdd burnin lvdd xo c d xreset vbusen ca3 nc nc nc cd12 cd15 clkin d e ca2 vss ca4 nc nc nc vss cd13 cd14 e f cvdd ca5 ca8 nc nc nc cd7 cd9 cd11 f g ca7 ca6 testen xcs xdack cd0 cd4 cd8 cd10 g h lvdd xint xwrl xrd cd1 cvdd cd6 atpgen lvdd h j nc vss xwrh xdreq cd2 cd3 cd5 vss nc j 123456789 top view figure 5-3 bga package terminal layout diagram (pfbga8ux81) 6. terminal functions S1R72V27 data sheet (rev. 1.00) epson 15 6. terminal functions osc qfp pin bga5 ball bga8 ball name i/o reset terminal type terminal description 58 b8 b9 xi in - analog internal oscillator circuit input (12 mhz, 24 mhz) 57 c8 c9 xo out - analog internal oscillator circuit output the clock inputs from the crystal oscillator and clkin for xi and xo are used exclusively by the register settings. fix xi at low when using clkin. test qfp pin bga5 ball bga8 ball name i/o reset terminal type terminal description 18 h1 g3 testen in (pd) (pd) test terminal (set to low) 40 h8 h8 atpgen in (pd) (pd) test terminal (set to low) 60 a8 c7 burnin in (pd) (pd) test terminal (set to low) usb qfp pin bga5 ball bga8 ball name i/o reset terminal type terminal description 67 a6 a7 r1 in - analog internal operation reference current setting terminal connect 6.2 kw 1% resistance between terminal and vss 73 a3 a4 dp bi hi-z analog usb port 0, data line (data +) 71 a4 a5 dm bi hi-z analog usb port 0, data line (data -) 3 b1 c1 vbusflg in (pu) schmitt (pu) usb power switch fault detection signal (1: normal, 0: error) 4 c1 d2 vbusen out lo 2ma usb power switch control signal 75 c3 b3 vbus in (pd) (pd) usb device bus detection signal pd: pull down pu: pull up 6. terminal functions 16 epson S1R72V27 data sheet (rev. 1.00) cpu i/f qfp pin bga5 ball bga8 ball name i/o reset terminal type terminal description bus mode ? strobe mode be mode 6 d1 d1 xreset in - schmitt reset signal 54 d8 d9 clkin in - - external clock input 23 g3 h4 xrd in - - read/strobe 25 h3 h3 xwrl (xwr) in - - write/strobe (lower) write/strobe 24 f3 j3 xwrh (xbeh) in - - write/strobe (upper) high-byte enable 22 h2 g4 xcs in - schmitt chip select signal 21 e3 h2 xint out high 2ma (tri-state) interrupt output signal 26 g4 j4 xdreq out high 2ma dma request 27 f4 g5 xdack in - - dma acknowledge 7 d2 c4 xbel in - - set to high or low low-byte enable 8 c4 c5 ca1 in - - 9 e1 e1 ca2 in - - 10 c5 d3 ca3 in - - 11 e2 e3 ca4 in - - 14 d3 f2 ca5 in - - 15 g1 g2 ca6 in - - 16 f1 g1 ca7 in - - 17 f2 f3 ca8 in - - cpu bus address 28 h4 g6 cd0 bi hi-z 2ma 29 g5 h5 cd1 bi hi-z 2ma 30 h5 j5 cd2 bi hi-z 2ma 34 f5 j6 cd3 bi hi-z 2ma 35 e6 g7 cd4 bi hi-z 2ma 36 h6 j7 cd5 bi hi-z 2ma 37 g6 h7 cd6 bi hi-z 2ma 38 f6 f7 cd7 bi hi-z 2ma 39 h7 g8 cd8 bi hi-z 2ma 43 g8 f8 cd9 bi hi-z 2ma 44 f7 g9 cd10 bi hi-z 2ma 47 e7 f9 cd11 bi hi-z 2ma 48 f8 d7 cd12 bi hi-z 2ma 49 d6 e8 cd13 bi hi-z 2ma 50 e8 e9 cd14 bi hi-z 2ma 51 c6 d8 cd15 bi hi-z 2ma cpu data bus the xint terminal can be set to 1/0 or hi-z/0 mode, dependi ng on register settings. note, however, that it cannot be pulled up with a voltage exceeding the rated value ev en in hi-z/0 mode, since it is not an open drain. the clock inputs from the crystal oscillator and clkin for xi and xo are used exclusively by the register settings. fix clkin at low when using xi and xo. pd: pull down pu: pull up 6. terminal functions S1R72V27 data sheet (rev. 1.00) epson 17 power qfp pin bga5 ball bga8 ball name voltage terminal description 5, 70, 74 a5, b3, c2 a3, a6, c2 hvdd 3.3v usb i/o power supply 13, 31, 46, 53 d7 c6, f1, h6 cvdd 1.8 to 3.3v cpu i/f i/o power supply 1, 19, 33, 42, 59, 65, 76 a2, a7, c7, g2 a2, a8, c3, c8, h1, h9 lvdd 1.8v osc i/o, test i/o, and internal power supply 2, 12, 20, 32, 41, 45, 55, 56, 66, 68, 72, 77 b2, b4, b5, b6, b7, g7 b1, b2, b4, b5, b6, b7, b8, e2, e7, j2, j8 vss 0v gnd 52, 61, 62, 63, 64, 69, 78, 79, 80 a1 a1, a9, d4, d5, d6, e4, e5, e6, f4, f5, f6, j1, j9 n.c. 0v nc terminal (connect to gnd) 7. electrical characteristics 18 epson S1R72V27 data sheet (rev. 1.00) 7. electrical characteristics 7.1 absolute maximum ratings item symbol rating units hvdd vss - 0.3 to 4.0 v cvdd vss - 0.3 to 4.0 v power supply voltage lvdd vss - 0.3 to 2.5 v hvi vss - 0.3 to hvdd + 0.5 v cvi*1 vss - 0.3 to cvdd + 0.5 v vvi*2 vss - 0.3 to 6.0 v input voltage lvi*3 vss - 0.3 to lvdd + 0.5 v hvo vss - 0.3 to hvdd + 0.5 v output voltage cvo*1 vss - 0.3 to cvdd + 0.5 v output current/terminal iout 10 ma storage temperature tstg -65 to 150 c *1 cpu-if *2 vbus *3 xi, testen, atpgen, burnin 7.2 recommended operating conditions item symbol min typ max units hvdd 3.00 3.30 3.60 v cvdd 1.65 - 3.60 v power supply voltage lvdd 1.65 1.80 1.95 v hvi -0.3 - hvdd+0.3 v cvi*1 -0.3 - cvdd+0.3 v vvi*2 -0.3 - 6.0 v input voltage lvi*3 -0.3 - lvdd+0.3 v ambient temperature ta -40 25 85 c *1 cpu-i/f *2 vbus *3 xi, testen, atpgen, burnin turn on power to the ic in the sequence shown below. lvdd (internal) hvdd, cvdd (io section) likewise, turn off power to the ic in the sequence shown below. hvdd, cvdd (io section) lvdd (internal) note: avoid leaving the hvdd or cvdd on continuously (for more than 1 second) when the lvdd is off, as doing so may affect chip reliability. 7. electrical characteristics S1R72V27 data sheet (rev. 1.00) epson 19 7.3 dc characteristics 7.3.1 current consumption item symbol condition min typ max units power supply feed current *1 power supply current iddh hvdd = 3.3v(typ) - 7.9 12.0 ma iddch cvdd = 3.3v(typ) - 1.6 5.0 ma iddcl cvdd = 1.8v(typ) - 0.7 2.0 ma iddl lvdd = 1.8v(typ) - 40.2 62.0 ma stationary current *2 power supply current idds vin = hvdd,cvdd,lvdd or vss hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v - - 25 a input leakage input leakage current il hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v hvih = hvdd cvih = cvdd lvih = lvdd vil = vss -5 - 5 a input leakage input leakage current (5 v tolerant) ilif hvdd = 3.0v cvdd = 1.65v lvdd = 1.65v hvoh = 5.5v -10 - 10 a *1: typ is the measured value when transferring data with the usb-hdd connected as the usb host. max is the value estimated from this value. *2: stationary current with ta = 25c and both terminals in input mode. 7. electrical characteristics 20 epson S1R72V27 data sheet (rev. 1.00) current consumption measurements for individual power management states using seiko epson operating conditions (ta = 25c) item condition typ units cpu_cut cpu bus operation *1 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v 4.2 uw sleep cpu bus operation *1 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v 8.8 uw active (when operating as usb device) (usb ? cpu-i/f) *2 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v 98 mw active (when operating as usb host) (usb ? cpu-i/f) *3 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v 118 mw *1: excluding current consumption due to dp pull- up resistance inside S1R72V27 (approx. 200 a). *2: when transferring data connected to a pc as a usb device (actual transfer rate 13.5 mb/s). *3: when transferring data with the usb-hdd connected as the usb host (actual transfer rate 13 mb/s). 7. electrical characteristics S1R72V27 data sheet (rev. 1.00) epson 21 7.3.2 input characteristics item symbol condition min typ max units input characteristics (lvcmos) terminal names: testen, atpgen, burnin h level input voltage vih1 lvdd = 1.95v 1.27 - - v l level input voltage vil1 lvdd = 1.65v - - 0.57 v input characteristics (lvcmos) terminal names: ca[8:1], cd[15:0], xrd, xwrl, xwrh, xbel, xdack, clkin h level input voltage vih2 cvdd=3.6v 2.2 - - v l level input voltage vil2 cvdd=3.0 - - 0.8 v h level input voltage vih3 cvdd=1.95v 1.27 - - v l level input voltage vil3 cvdd=1.65v - - 0.57 v schmitt input characteristics (usb fs) terminal names: dp, dm h level trigger voltage vt+ (usb) hvdd = 3.6v 1.1 - 1.8 v l level trigger voltage vt- (usb) hvdd = 3.0v 1.0 - 1.5 v hysteresis voltage v (usb) hvdd= 3.0v 0.1 - - v input characteristics (usb fs differential) terminal names: dp, dm pair hvdd = 3.0v differential input voltage - - 0.2 v differential input sensitivity vds (usb) 0.8v to 2.5v input characteristics (vbus) terminal names: vbus h level trigger voltage vt+(vbus) hvdd = 3.6v 1.86 - 2.85 v l level trigger voltage vt- (vbus) hvdd = 3.0v 1.48 - 2.23 v hysteresis voltage v (vbus) hvdd= 3.0v 0.31 - 0.64 v input characteristics (schmitt) terminal names: vbusflg h level trigger voltage vt1+ hvdd = 3.6v 1.4 - 2.7 v l level trigger voltage vt1- hvdd = 3.0v 0.6 - 1.8 v hysteresis voltage v hvdd= 3.0v 0.3 - - v input characteristics (schmitt) terminal names: xcs, xreset h level trigger voltage vt1+ cvdd=3.6v 1.4 - 2.7 v l level trigger voltage vt1- cvdd=3.0v 0.6 - 1.8 v hysteresis voltage v1 cvdd=3.0v 0.3 - - v h level trigger voltage vt2+ cvdd=1.95v 0.6 - 1.4 v l level trigger voltage vt2- cvdd=1.65v 0.3 - 1.1 v hysteresis voltage v2 cvdd=1.65v 0.2 - - v input characteristics terminal names: vbusflg pull-up resistor rplu2h vi=vss 50 100 240 k ? input characteristics terminal names: vbus pull-down resistor rpld3l vi=5.0v 110 125 150 k ? input characteristics terminal names: atpgen, burnin pull-down resistor rpld1l vi=lvdd 24 60 150 k ? input characteristics terminal names: testen pull-down resistor rpld2l vi=lvdd 48 120 300 k ? 7. electrical characteristics 22 epson S1R72V27 data sheet (rev. 1.00) 7.3.3 output characteristics item symbol condition min typ max units output characteristics terminal names: cd[15:0], xdreq, xint h level output voltage voh1 cvdd = 3.0v ioh = -2ma cvdd-0.4 - - v l level output voltage vol1 cvdd = 3.0v iol = 2ma - - vss+0.4 v h level output voltage voh2 cvdd = 1.65v ioh = -1ma cvdd-0.4 - - v l level output voltage vol2 cvdd = 1.65v iol = 1ma - - vss+0.4 v l level output voltage vol2(2) cvdd = 1.65v iol = 0.8ma - - vss+0.3 v output characteristics terminal names:vbusen h level output voltage voh4 hvdd = 3.0v ioh = -2ma hvdd-0.4 - - v l level output voltage vol4 hvdd = 3.0v iol = 2ma - - vss+0.4 v output characteristics (usb fs) terminal names: dp, dm h level output voltage voh(usb) hvdd=3.0v 2.8 - - v l level output voltage vol(usb) hvdd=3.6v - - 0.3 v output characteristics (usb hs) terminal names: dp, dm h level output voltage vhsoh (usb) hvdd = 3.0v 360 - - mv l level output voltage vhsol (usb) hvdd = 3.6v - - 10.0 mv output characteristics terminal names: cd[15:0], xint off-state leakage current ioz cvdd = 3.6v cvoh = cvdd vol = vss -5 - 5 a 7. electrical characteristics S1R72V27 data sheet (rev. 1.00) epson 23 7.3.4 terminal capacitance item symbol condition min typ max units terminal capacitance terminal name: all input terminals input terminal capacitance ci f = 10mhz hvdd = cvdd = lvdd = vss - - 8 pf terminal capacitance terminal name: all output terminals output terminal capacitance co f = 10mhz hvdd = cvdd = lvdd = vss - - 8 pf terminal capacitance terminal name: all input/output terminals (except dp, dm) input/output terminal capacitance 1 cio1 f = 10mhz hvdd = cvdd = lvdd = vss - - 8 pf terminal capacitance terminal names: dp, dm input/output terminal capacitance 2 cio2 f = 10mhz hvdd = cvdd = lvdd = vss - - 11 pf 7. electrical characteristics 24 epson S1R72V27 data sheet (rev. 1.00) 7.4 ac characteristics 7.4.1 reset timing xreset treset code description min typ max units treset reset pulse width 40 - - ns 7.4.2 clock timing 7. electrical characteristics S1R72V27 data sheet (rev. 1.00) epson 25 7. electrical characteristics 26 epson S1R72V27 data sheet (rev. 1.00) 7.4.3 cpu/dma i/f access timing 7.4.3.1 specifications fo r cvdd = 1.65 v to 3.6 v xdreq(o) xdack(i) xcs i xrd i cd o valid tcas ca i xwrh/l i xwr cd i code tcas tccs min 6 6 typ - - max - - unit ns ns tcch tcah 6 6 - - - - ns ns trbd 1 - - ns trdf - - 33 ns trdh 2 - - ns trbh - - 6 ns twds twdh - 6 - - 10 - ns ns tdrn - - 35 ns tdaa tdng 6 nn *16.6 - - - - ns ns tcah tccs tcch trbd trdf trdh trbh twds twdh tdrn tdaa tdan write read tras tras 35 - - ns twas 35 - - ns twas trng twng twcy trcy trcy 55 - - ns trng 20 - - ns 55 - - ns twcy 20 - - ns twng xbeh/l(i) twbs twbh twbs twbh 6 6 - - - - ns ns write byte enable hold time (cl=30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data delay acknowledge time write data hold time (after strobe negation) xdreq negate delay time xdack setup time xdreq minimum negate time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time tccn tccn 15 - - ns xcs negate time (only when cpuif mode is set*) *nn is determined by the dma_edgemode.negcontrol[3:0] setting. nn = (negcontrol + 3) tdng tdan 6 - - ns xdack hold time 7. electrical characteristics S1R72V27 data sheet (rev. 1.00) epson 27 7.4.3.2 specific ations when limited to cvdd = 3.0 v to 3.6 v (relaxed specifications) xdreq(o) xdack(i) xcs i xrd i cd o valid tcas ca i xwrh/l i xwr cd i code tcas tccs min 6 6 typ - - max - - unit ns ns tcch tcah 6 6 - - - - ns ns trbd 1 - - ns trdf - - 30 ns trdh 2 - - ns trbh - - 6 ns twds twdh - 6 - - 10 - ns ns tdrn - - 30 ns tdaa tdng 6 nn *16.6 - - - - ns ns tcah tccs tcch trbd trdf trdh trbh twds twdh tdrn tdaa tdan write read tras tras 33 - - ns twas 33 - - ns twas trng twng twcy trcy trcy 55 - - ns trng 20 - - ns 55 - - ns twcy 20 - - ns twng xbeh/l(i) twbs twbh twbs twbh 6 6 - - - - ns ns write byte enable hold time (c l =30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data delay acknowledge time write data hold time (after strobe negation) xdreq negate delay time xdack setup time xdreq minimum negate time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time tccn tccn 15 - - ns xcs negate time (only when cpu if mode is set*) *nn is determined by the dma_edgemode.negcontrol[3:0] setting. nn = (negcontrol + 3) tdng tdan 6 - - ns xdack hold time 7. electrical characteristics 28 epson S1R72V27 data sheet (rev. 1.00) 7.4.4 usb i/f timing complies with the usb 2.0 standard (universal serial bus specification revision 2.0 released on april 27, 2000). 8. connection examples S1R72V27 data sheet (rev. 1.00) epson 29 8. connection examples 8.1 cpu i/f connection example ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq *1 xdack *2 xint address[8:1] data[15:0] xcs xrd xwrh xwrl xdreq xdack xint ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq *1 xdack *2 xint address[8:1] data[15:0] xcs xrd xbeh xwr xdreq xdack xint xbel 16-bit cpu (xwrh/xwrl) connection example *1: open when dma is not used *2: set to inactive level when dma is not used 16-bit cpu (xbeh/xbel) connection example *1: open when dma is not used *2: set to inactive level when dma is not used 8. connection examples 30 epson S1R72V27 data sheet (rev. 1.00) 8.2 usb i/f connection example refer to the separately provided s1r72v series usb 2.0 hi-speed pcb design guidelines. 9. product codes S1R72V27 data sheet (rev. 1.00) epson 31 9. product codes table 9-1 product codes product code product type S1R72V27b05**** pfbga5ux60 package S1R72V27b08**** pfbga8ux81 package S1R72V27f14**** qfp14-80 package 10. external dimension diagrams 32 epson S1R72V27 data sheet (rev. 1.00) 10. external dimension diagrams refer to the pfbga5ux60, pfbga8ux81 and qfp14-80 package drawings at the end of this document. revision history revision history revision details date rev. page (old issue) type details 11/20/2007 1.0 all new newly established a1 corner 1 a bottom view a1 corner top view s s d e a e b x y 1 0.23 0.25 0.25 0.26 0.5 0.36 0.08 0.1 d e symbol a min - 5 5 nom max 1.2 d e a a 1 e s d ? e p-tfbga-060-0505-0.50(pfbga5u-60) 2900-0002-01(rev.1.1) s e - - - - - - - - - - - - - - - - - - 2 3 4 5 6 7 8 b c d e f g h index - - - a1 corner 3 2 1 4 8 7 6 5 9 h a c d e f g b j bottom view index a1 corner top view z z d e a e b x y 1 0.3 0.8 0.8 0.38 0.8 0.48 0.08 0.1 d e symbol a min 8 8 nom max 1.2 d e a e e a 1 z d z e 2900-0002-01(rev.1.1) p-tfbga-081-0808-0.80(pfbga8u-81) - - - - - - - - - - - - - - - - - - - international sales operations america epson electronics america, inc. headquarters 2580 orchard parkway san jose , ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre , 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, ta i p e i 11 0 phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg ., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 411338400 first issue december 2007 |
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